Scribble at 2022-11-15 15:50:26 Last modified: unmodified
Intrusion Detection and Prevention Systems (IDS/IPS) are among the most demanding stateful network functions. Today's network operators are faced with securing 100Gbps networks with 100K+ concurrent connections by deploying IDS/IPSes to search for 10K+ rules concurrently. In this paper we set an ambitious goal: Can we do all of the above in a single server? Through the Pigasus IDS/IPS, we show that this goal is achievable, perhaps for the first time, by building on recent advances in FPGA-capable SmartNICs. Pigasus' design takes an FPGA-first approach, where the majority of processing, and all state and control flow are managed on the FPGA. However, doing so requires careful design of algorithms and data structures to ensure fast common-case performance while densely utilizing system memory resources. Our experiments with a variety of traces show that Pigasus can support 100Gbps using an average of 5 cores and 1 FPGA, using 38x less power than a CPU-only approach.
abstract だけでも分かるんだけど、実際にプレゼンテーションを見ても「おいっ」と突っ込みたくなるような発表だ。そら、FPGA（後からプログラミング可能な CPU）のレベルで処理を最適化したらパフォーマンスの向上は（何倍になるかはともかく）できるに決まってるだろう。Snort を出して比較してるから、てっきり何か根本的に異なる設計思想の IDS が登場するのかと思ったら、ハードウェアを最適化しましたってだけだ。カーネギー・メロンも、大したことないな。